1. Field of the Invention
This invention relates to floating point multipliers and, more particularly, to methods and apparatus for increasing the speed of rounding in such multipliers.
2. History of the Prior Art
Various arrangements for providing fast multiplying circuits for use in computers have been proposed. Basically, the product of two n-bit binary operands is realized by determining a number of partial products each of which is offset by one bit to the left from the preceding partial product. The partial products are then summed to reach a result. In order to rapidly sum the partial products, binary tree arrangements have been suggested in which the individual partial products are grouped in pairs and the groups summed in parallel by carry-save adders. The results of the summations of these partial products are again grouped in pairs and the groups summed in parallel in the same manner by additional carry-save adders. This process continues until the last two partial products are summed to produce a product. High Speed Multiplier Using a Redundant Binary Adder Tree, Harata et al, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 1, February 1987, describes such a circuit. A carry propagate adder may used to add the sums and the carries of the last two partial products from the preceding stages of the binary tree multiplier.
These circuits may be used in either integer multiplication or in generating the mantissa in floating point multiplication. When the multiplier circuit is used in a floating point multiplier arrangement, it typically produces a result which has twice as many bits as the machine handles so it is often necessary for the result to be rounded. For example, the standard for double precision binary numbers requires fifty-three bits. A product of two fifty-three bit binary numbers is one hundred and six bits long. However, a double precision result uses only the upper fifty-four bits of this product with the most significant bit indicating overflow. The lower fifty-three bits are necessary only to determine whether a carry is generated from the lower bits, whether rounding is required, and the precise rounding value.
In order to accomplish rounding of the product, it is first necessary to normalize the mantissa. In binary multiplication using two normalized operands, this requires at most a shift to the right of the mantissa by one bit so that only a single significant bit lies to the left of the binary point and an increase in the power of the exponent. Until the mantissa is normalized, the bit position at which rounding is accomplished is not known. Even though the lower order bits of the product are used only to generate a carry and to determine rounding, the generation of the carry result for the lower order bits is required before the carry propagate adder for the upper order bits can begin operation. Since a mantissa is derived and can be normalized only after the carry propagate addition of the upper order bits is complete, the entire operation must typically wait for the low order carry to be generated and for that carry bit to propagate across the upper bits. Thus, the carry from the lower order bits is in the critical path.
It is typical in such multipliers once normalization has occurred to generate the rounding condition, and, if necessary, add a one to the normalized mantissa at the least significant bit to produce the rounded result. This approach uses a carry propagate adder at the output of the multiplier tree and an incrementer at the output of the adder to produce the rounding. A common approach to speed the operation of the arrangement is to use two rounding circuits in parallel. One circuit presumes the mantissa will overflow while the other assumes it will not. The correct result is selected once the most significant bit of the unrounded mantissa is available.
In any case, in the typical prior art floating point multiplier everything awaits the result of the carry propagation of the lower order bits.